1. Field of the Invention
This invention relates to improvements in digital-to-analog converters, and more particularly to improvements in digital-to-analog converters of the current-summing type in which binary weighted current sources are switched by a digital input code and summed at the same node.
2. Relevant Background
A simplified electrical schematic diagram of a typical digital-to-analog converter 10 using ratioed current sources, according to the prior art, is shown in FIG. 1. An operational amplifier 11 along with an input resistor 12 of value R0 and two reference voltages, VRF1 and VRF2, servo the current through a cascode transistor 15 to equal: ##EQU1## This well-known arrangement, used extensively in many state-of-the-art digital-to-analog converters, insures that the switched currents, which are summed together on summing nodes S+and S-, are all proportional to I.sub.ref. The summing nodes S+and S- are connected to respective output load resistors 16 and 17 of equal value, RL. The output load resistors 16 and 17 are of the same type as the input resistor 12. Thus, the voltage difference across the output load resistors 16 and 17 forms an output that is proportional to the difference in the reference voltages, VRF2-VRF1. Choosing temperature-stable reference voltages for VRF2 and VRF1 therefore guarantees an equally stable output voltage for the digital-to-analog converter 10.
The digital-to-analog converter 10 has k cells 20, 21, . . . 23, k being the number of bits of a digital input word or signal to be converted. Each bit k has a corresponding current of value 2.sup.(k-n) I.sub.ref flowing from the collector of the transistor in the differential pair that is switched on in its respective cell. For correct matching, a resistor is usually connected between the emitter of each transistor, Q(k), and ground. A constant voltage drop across each resistor is chosen to be large enough to make the effect of V.sub.be mismatches smaller than that of mismatches between the resistors. Also, usually the resistors can be laid out with better relative accuracy than the transistors.
Each cell has a respective resistor of value 2.sup.(n-k) R, with R chosen such that the MSB current of cell 20 is In=I.sub.ref. To keep equal current densities in all devices, emitter area scaling is necessary in the transistors Q(k) and their corresponding cascode differential pairs. Thus, for an n bit converter, in the fabrication of the MSB cell 20, n transistors should theoretically be connected in parallel to form the transistor Q(n) and the devices of the associated differential pair; in the fabrication of the next cell 21, n-1 transistors should theoretically be connected in parallel to form the transistor Q(n-1) and its differential pair, and so on. However, as the number of bits increases, the number of transistors necessary to carry out the circuit increases geometrically, and becomes impractically high above five or six bits. This necessitates added design measures be taken to reduce the total size of the circuit.
Until now, no method that is known by applicant generates the weighted currents in a systematic way without requiring a large array of transistors with scaled emitter areas. Most existing circuits are derived from FIG. 1, and silicon area is usually kept down by series division of currents, carried out by resistive current dividers or segmented structures. Another drawback of the classical approaches is the need for an operational amplifier to generate the circuit biasing, which comes at the expense of total circuit area and speed.